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FEATURES

LTC3543 600mA Synchronous Step Down Buck Regulator with PLL, Soft-Start and Spread Spectrum DESCRIPTIO
The LTC(R)3543 is a high efficiency monolithic synchronous current mode buck regulator. The switching frequency is internally set at 2.25MHz, allowing the use of small surface mount inductors and capacitors. In PLL mode, the LTC3543 can acquire frequencies between 1MHz and 3MHz. Also, the LTC3543 has spread spectrum capability providing a lower noise regulated output, as well as low noise at the input. In Burst Mode(R) 0peration, the supply current is only 45A, dropping to <1A in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3543 ideally suited for single Li-Ion battery-powered applications. The 100% duty cycle provides a low dropout operation, extending the battery life in portable systems. Burst Mode operation increases efficiency at light loads, further extending battery life. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.

600mA Output Current 2.5V to 5.5V Input Voltage Range 2.25MHz Constant Frequency Operation, Spread Spectrum or Synchronized PLL (1MHz to 3MHz) High Efficiency: Up to 95% 1A Peak Inductor Current Very Low Quiescent Current: Only 45A During Burst Mode Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle Overtemperature Protected Stable with Ceramic Capacitors Shutdown Mode Draws <1A Supply Current 2% Output Voltage Accuracy Current Mode Operation for Excellent Line and Load Transient Response Soft-Start Available in a Low Profile (0.75mm) 2mm x 3mm 6-Lead DFN Package
APPLICATIO S

Portable Instruments Cellular Phones
TYPICAL APPLICATIO
2.5V TO 5.5V 10F LTC3543 PWR_EN MODE RUN VFB VIN SW
Efficiency and Power Loss vs Load Current
3.3H 100 1.5V 300k 10pF 10F EFFICIENCY (%) VOUT 1.5V 90 80 70 60 50 40 30 EXPOSED PAD MODE = VIN PULSE SKIP MODE = VFB PULSE SKIP WITH SPREAD SPECTRUM MODE = GND BURST MODE MODE = EXTERNAL CLOCK PLL
3543 TA01
VIN = 2.7V VIN = 4.2V 100 POWER LOSS (mW)
MODE CAP GND
4nF
200k
20 10 0 0.1 Burst Mode ENABLED 1 10 100 LOAD CURRENT (mA)
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1000
VIN = 3.6V
10 POWER LOSS AT VIN = 3.6V
10
0.1 1000
3543 TA01b
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LTC3543 ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW RUN VFB VIN 6 5 4
VIN Voltage ................................................... -0.3V to 6V RUN, VFB, MODE, CAP Voltages...................-0.3V to VIN SW Voltage ....................................-0.3V to (VIN + 0.3V) Operating Temperature Range (Note 2) ... -40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range................... -65C to 125C
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1 SW
2 CAP
3 MODE
DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN PIN 7 IS GND
TJMAX = 125C, JA = 64C/W
ORDER PART NUMBER LTC3543EDCB
DCB PART MARKING LCCK
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL RUN VFB IVFB IPK VLOADREG VLINEREG VIN IS PARAMETER Run Threshold Regulated Feedback Voltage Feedback Pin Current Peak Inductor Current Output Voltage Load Regulation Output Voltage Line Regulation Input Voltage Range Input DC Bias Current Active Mode Sleep Mode Shutdown Nominal Oscillator Frequency RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.6V unless otherwise noted.
CONDITIONS (Note 4) VIN = 3.6V, VFB = 0V (Note 4)

MIN 0.3 0.588 0.7
TYP 1 0.6 1 0.5
MAX 1.5 0.612 1 1.3 0.5
UNITS V V A A %/mA %/V V A A A MHz
2.5 375 45 0.1
5.5 500 70 1
(Note 5) VOUT = 90%, ILOAD = 0A VOUT = 103%, ILOAD = 0A VRUN = 0V, VIN = 5.5V
fOSC RPFET RNFET ISW
1.80
2.25 0.45 0.35 1
ISW = 100mA ISW = 100mA VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3543E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls.
Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD)(64C/W) Note 4: The LTC3543 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. This test mode is equivalent to continuous mode operation. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency.
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LTC3543 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage (VIN)
100 IOUT = 200mA 90 EFFICIENCY (%) 80 70 IOUT = 10mA 60 50 40 VOUT = 1.8V 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 5.5
3543 G01
EFFICIENCY (%)
EFFICIENCY (%)
IOUT = 600mA
Power Loss vs Load Current
500 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V EFFICIENCY (%) 100 90 80 70 300 60 50 40 30 100 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3543 G04
400 POWER LOSS (mW)
EFFICIENCY (%)
200
RDS(ON) vs Input Voltage (VIN)
500 450 400 350 RDS(ON) (m) 300 250 200 150 100 50 0 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5
3543 G07
MAIN SWITCH RDS(ON) (m)
VIN = 3.6V
RDS(ON) (m)
SYNCHRONOUS SWITCH
UW
TA = 25C unless otherwise noted. (From Figure 1a)
Efficiency vs Load Current
100 90 80 70 60 50 40 30 20 10 0 0.1 VOUT = 1.2V 1 10 100 LOAD CURRENT (mA) 1000
3543 G02
Efficiency vs Load Current
100 90 80 Burst Mode ENABLED VIN = 4.2V
Burst Mode ENABLED
VIN = 2.7V
VIN = 4.2V
70 60 50 40 30 20 10 0 0.1 VIN = 2.7V
VIN = 3.6V
VIN = 3.6V
VOUT = 1.5V 1 10 100 LOAD CURRENT (mA) 1000
3543 G03
Efficiency vs Load Current
Burst Mode ENABLED 100 90 80 VIN = 4.2V 70 60 50 40 30 VIN = 2.7V VOUT = 1.8V 1 10 100 LOAD CURRENT (mA) 1000
3543 G05
Efficiency vs Load Current
Burst Mode ENABLED
VIN = 4.2V
VIN = 3.6V
VIN = 3.6V
20 10 0 0.1 1
VIN = 2.7V VOUT = 2.5V 10 100 LOAD CURRENT (mA) 1000
3543 G06
0 0.1
Main Switch Resistance vs Temperature
500 450 400 350 300 250 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G08
Synchronous Switch Resistance vs Temperature
500 450 400 VIN = 3.6V 350 300 VIN = 4.2V 250 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G09
VIN = 2.7V
VIN = 2.7V
VIN = 4.2V
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LTC3543 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25C unless otherwise noted.
Switching Frequency vs Input Voltage (VIN)
2.8 2.7 SWITCHING FREQUENCY (MHz) SWITCHING FREQUENCY (MHz) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5
3543 G10
2.25 2.20 2.15 2.10 2.05 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G11
LOAD CURRENT (mA)
Feedback Voltage (VFB) vs Input Voltage (VIN)
612 610 608 FEEDBACK VOLTAGE (mV) 606 604 602 600 598 596 594 592 590 588 2.5 3.0 4.5 4.0 3.5 INPUT VOLTAGE (V) 5.0 5.5
3543 G13
FEEDBACK VOLTAGE (mV)
606 604 602 600 598 596 594 592 590 588 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G14
LEAKAGE CURRENT (pA)
Dynamic Supply Current vs Input Voltage (VIN)
400 ILOAD = 0A VOUT = 1.5V SUPPLY CURRENT (A) PULSE SKIP MODE 400 350
LEAKAGE CURRENT (pA)
SUPPLY CURRENT (A)
300
200
100 Burst Mode OPERATION
0 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 5.5
3543 G16
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UW
Switching Frequency vs Temperature
2.40 2.35 1.54 2.30 VIN = 3.6V 1.56
Output Voltage vs Load Current
1.52
1.50 VIN = 2.7V 1.48 VIN = 3.6V VIN = 4.2V 0 200 600 800 400 OUTPUT VOLTAGE (V) 1000
3543 G12
1.46
Feedback Voltage (VFB) vs Temperature
612 610 608 VIN = 3.6V 800 700 600 500
Switch Leakage (ISW) vs Temperature
VIN = 5.5V RUN = 0V
SYNCHRONOUS SWITCH 400 300 200 MAIN SWITCH 100 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G15
Dynamic Supply Current vs Temperature
1000 900 800 700 600 500 400 300 200 100 0
Switch Leakage (ISW) vs Input Voltage (VIN)
RUN = 0V
300 250 200 150 100 50 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
3543 G17
MAIN SWITCH SYNCHRONOUS SWITCH
2.5
3.0
4.0 4.5 3.5 INPUT VOLTAGE (V)
5.0
5.5
3543 G18
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LTC3543 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25C unless otherwise noted.
Startup from Shutdown
RUN 5V/DIV VOUT 1V/DIV INDUCTOR CURRENT 200mA/DIV 200s/DIV VOUT AC COUPLED 50mV/DIV SW 5V/DIV IL 100mA/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 300mA
3543 G19
Load Step
VOUT AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV 20s/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 0V
3543 G22
Spread Spectrum Load Step
VOUT AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 100mA TO 200mA VMODE = 0.6V 10s/DIV
3543 G25
UW
Pulse Skip Operation
VOUT AC COUPLED 50mV/DIV SW 5V/DIV IL 100mA/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA VMODE = 3.6V 10s/DIV
3543 G20
Burst Mode Operation
VIN = 3.6V VOUT = 1.5V ILOAD = 3mA VMODE = 0V
10s/DIV
3543 G21
Load Step
VOUT AC COUPLED 200mV/DIV IL 200mA/DIV ILOAD 200mA/DIV 20s/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 3.6V
3543 G24
Load Step
VOUT AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV 10s/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 100mA TO 600mA VMODE = 3.6V
3543 G23
PLL Operation
VC1 200mV/DIV VMODE 2V/DIV
PLL Operation at 3MHz
SW 2V/DIV 100s/DIV C1 = 4F 3MHz TO 1MHz STEP 100ns/DIV
3543 G26
3543 G27
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LTC3543 PI FU CTIO S
SW (Pin 1): Switch Node Connector to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. CAP (Pin 2): Capacitor used for smoothing out spread spectrum or for PLL response. Connect to a capacitor whose other plate is connected to GND, or allow the pin to float. Value = 1nF - 10nF. MODE (Pin 3): Mode Selection Pin. Connect as follows to invoke desired operation: MODE = GND Burst Mode, MODE = VFB Pulse skip with spread spectrum, MODE = VIN Pulse skip, MODE = External clock PLL mode. VFB (Pin 4): Feedback sensing pin for the external feedback resistors. RUN (Pin 5): Run Control Input. Forcing pin above 1.5V enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled, drawing <1A of supply current. Do not leave the RUN pin floating. VIN (Pin 6): Main Supply Pin. Exposed Pad (Pin 7): Exposed Pad connected to ground.
FU CTIO AL DIAGRA
VOUT R2 VFB 4 R1 0.6V
OSC
CAP 2
C1
PLL
MODE 3 RUN 5
MODE SELECT
6
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VIN 6 PEAK CURRENT LEVEL REF RS CIN VIN
EA
ICOMP S R Q QB L LOGIC L SYNCHRONOUS 1 BP MAIN SW L VOUT COUT
SPREAD SPECTRUM
BURST
IRCMP 7
GND
3543 FD
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LTC3543 OPERATIO
Main Control Loop The LTC3543 uses current mode step-down architecture with both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches internal. During normal operation, the internal top power MOSFET is turned on each cycle as the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier, EA. When the load current increases, it causes a slight decrease in the feedback voltage, VFB, relative to an internal reference voltage which, in turn, causes the EA amplifier's output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Burst Mode Operation The LTC3543 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. Burst Mode operation is enabled by connecting the MODE pin to ground. During Burst Mode operation, the LTC3543's internal circuits sense when the inductor peak current falls below 100mA. When below this level, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 45A, and holding the peak current reference level at 100mA. The LTC3543 remains in this sleep state until the feedback voltage falls below its internal reference. Once this occurs, the regulator wakes up and allows the inductor to develop 100mA current pulses. In light loads, this will cause the output voltage to increase and the internal peak current reference to decrease. When the peak current reference falls to below 100mA, the part re-enters sleep mode and the cycle is repeated. This process repeats at a rate dependent on the load demand. Pulse Skip Mode Operation Connecting the MODE pin to VIN places the LTC3543 in pulse skip mode. During light loads, the inductor can reach zero amps or reverse current on each pulse. This
AMPLITUDE (dBm)
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(Refer to Functional Diagram)
is caused by the bottom MOSFET being turned off by the current reversal comparator, IRCMP, at which time the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for a switching regulator. At very light loads, the LTC3543 will automatically skip pulses in order to maintain output regulation. Spread Spectrum Operation Setting the MODE pin from 0.55V to 0.8V will place the part in pulse skip mode with spread spectrum; an easy way to do this is to connect the MODE pin to the VFB pin. In this mode, an external capacitor is required between CAP and GND. The external capacitor assists in smoothing frequency transitions. The spread spectrum architecture randomly varies the LTC3543's switching frequency from 2MHz to 3MHz, significantly reducing the peak radiated and conducting noise on both the input and output supplies, making it easier to comply with electromagnetic interference (EMI) standards. Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or constant, based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). Figure 1a depicts the output noise spectrum
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 2.0 2.2 2.6 2.4 FREQUENCY (MHz) 2.8 3.0
3543 F01a
RBW = 3kHz
Figure 1a. Output Noise Spectrum of Conventional Buck Switching Converter (LTC3543 with Spread Spectrum Disabled) Showing Fundamental and Harmonic Frequencies
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LTC3543 OPERATIO
-10 -20 -30 AMPLITUDE (dBm) -40 -50 -60 -70 -80 -90 -100 -110 2.0 2.2 2.6 2.4 FREQUENCY (MHz) 2.8 3.0
3543 F01b
RBW = 3kHz
Figure 1b. Output Noise Spectrum of the LTC3543 Spread Spectrum Buck Switching Converter. Note the Reduction in Fundamental and Harmonic Peak Spectral Amplitude Compared to Figure 1a.
of a conventional buck switching converter (LTC3543 with spread spectrum operation disabled) with VIN = 3.6V, VOUT = 1.5V and IOUT = 300mA. Unlike conventional buck converters, the LTC3543's internal oscillator is designed to produce a clock pulse whose frequency is randomly varied between 2MHz and 3MHz. This has the benefit of spreading the switching noise over a range of frequencies, significantly reducing the peak noise. Figure 1b shows the output noise spectrum of the LTC3543 (with spread spectrum operation enabled) with VIN = 3.6V, VOUT = 1.5V and IOUT = 300mA. Note the significant reduction in peak output noise ( 20dBm). Phase-Locked Loop Operation A phase-locked loop (PLL) is available on the LTC3543 to synchronize the internal oscillator to an external clock source that is connected to the MODE pin. In this case, an external capacitor should be connected between the CAP pin and GND to serve as part of the PLL's loop filter. The LTC3543's phase detector adjusts the voltage on the CAP pin to align the turn-on of the internal P-channel MOSFET to the rising edge of the synchronizing signal. Note that when the MODE pin is not being driven by an external clock source, the MODE pin must be held to one of the following voltage potentials: VIN, GND, or VFB. The typical capture range of the LTC3543 's PLL is guaranteed over temperature to be 1MHz to 3MHz. In other words, the LTC3543's PLL is guaranteed to lock to an
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external clock source whose frequency is between 1MHz and 3MHz. Selecting the switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. Note that the PLL is inhibited during soft-start and uses the internal 2.25MHz frequency until regulation is established. Also the regulator is in pulse skip mode during PLL operation. Short-Circuit Protection When the output is shorted to ground, the LTC3543 senses the high inductor current and disallows the main power FET from turning on. The main FET is held off until the inductor current decays to a normal level. Dropout Operation Depending upon the external feedback resistor ratio, it is possible for VIN to approach the output voltage level. As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3543 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Low Supply Operation The LTC3543 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 2 shows the reduction in the maximum output current as a function of input voltage for various output voltages.
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LTC3543 OPERATIO
Slope Compensation and Inductor Peak Current Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%; however, the LTC3543 uses a patent-pending scheme that counteracts this compensating ramp, allowing the maximum inductor peak current to remain unaffected throughout all duty cycles.
MAXIMUM OUTPUT CURRENT (mA)
APPLICATIO S I FOR ATIO
The basic LTC3543 application circuit is shown on the front page of this datasheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 4.7H. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current, and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current, as shown in Equation 1. A reasonable starting point for setting ripple current is IL = 130mA 20% ILOADMAX. IL = VOUT f *L V * 1 - OUT VIN (1)
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 665mA rated inductor should be enough for most applications (600mA + 65mA). For better efficiency, choose a low DC-resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 100mA. Lower inductor values (higher IL) will cause this to occur
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1500 1400 1300 1200 1100 1000 900 800 700 600 500 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5
3543 F02
VOUT = 1.2V
VOUT = 1.5V
Figure 2. Maximum Output Current vs Input Voltage (VIN)
at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements, and any radiated field/EMI requirements, than on what the LTC3543 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3543 applications. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
CIN required IRMS IOMAX * [VOUT (VIN -VOUT )]1/2 VIN
(2)
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LTC3543 APPLICATIO S I FOR ATIO
Table 1. Representative Surface Mount Inductors
MANUFACTURER TDK PART NUMBER VLF3010AT-2R2M1R0 VLF3012AT-2R2M1R0 VLCF4020T-2R2N1R7 VLCF5020-2R7N1R7 VLCF5020-3R3N1R6 VLCF5020-4R7N1R4 Sumida Taiyo Yuden CoEv CDRH2D18/HP-2R2NC NR4018T4R7M NP03SB4R7M DN4835-2R2 DN4835-3R3 DN4835-6R8 muRata LQH32CN2R2M33 LQH55DN2R2M03 LQH55DN3R3M03 LQH55DN4R7M03 VALUE (H) 2.2 2.2 2.2 2.7 3.3 4.7 2.2 4.7 4.7 2.2 3.3 6.8 2.2 2.2 3.3 4.7 MAX DC CURRENT (A) 1.0 1.0 1.7 1.7 1.6 1.4 1.6 1.7 1.2 2.6 2.43 1.41 0.79 3.2 2.9 2.7 DCR (m) 100 88 54 58 69 79 48 90 47 47 58 117 97 29 36 41 HEIGHT (mm) 1.0 1.2 2.0 2.0 2.0 2.0 2.0 1.8 1.8 3.5 3.5 3.5 3.2 4.7 4.7 4.7
This formula has a maximum of VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there are any questions. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple VOUT is determined by: 1 VOUT IL ESR + 8 fCOUT
where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of
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tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include the Sanyo POSCAP, the Kemet T510 and T495 series, and the Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. C1 Selection When spread spectrum operation is enabled, the frequency of the LTC3543 is randomly varied over the range of frequencies between 2MHz and 3MHz. In this case, a capacitor should be connected between the CAP pin and GND to smooth out the changes in frequency. This not only provides a smoother frequency spectrum but also ensures that the switching regulator remains stable by preventing abrupt changes in frequency. When the PLL mode is enabled, if the external clock frequency is greater than the internal oscillator's frequency (OSC), then current is sourced continuously, pulling up the voltage on the CAP pin. If the external clock frequency is less than OSC, current is sunk continuously, pulling down the voltage on the CAP pin. When the external and internal
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(3)
LTC3543 APPLICATIO S I FOR ATIO
frequencies are the same but exhibit a phase difference, current pulses (sourcing or sinking) are used for an amount of time corresponding to the phase difference. The current pulses adjust the voltage on the CAP pin until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the CAP pin is high impedance and the external capacitor holds the voltage. The external cap is used by the PLL's loop filter to help smooth out the voltage change and provide a stable input to the voltage-controlled oscillator. The value of C1 will determine how fast the loop acquires lock. Typically C1 is 1nF to 10nF in PLL mode. A value of 2.2nF is suitable in most applications. Using Ceramic Capacitors for CIN, COUT and C1 High value, low cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3543's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. This ringing can couple to the output and be mistaken as loop instability. Even worse, the sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
0.6V VOUT < 5.5V R2 VFB LTC3543 GND
3543 F03
POWER LOSS (mW)
R1
Figure 3. Setting Output Voltage
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Output Voltage Programming The output voltage is set by a resistor divider according to the following formula: R2 VOUT = 0 . 6 V * 1 + R1 (4) The external resistor divider is connected to the output allowing remote voltage sensing as shown in Figure 3. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3543 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 4.
500 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 400 300 200 100 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3543 F04
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Figure 4. Power Loss vs Load Current
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LTC3543 APPLICATIO S I FOR ATIO
1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP * DC) + (RDS(ON)BOT * (1 - DC)) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Thermal Considerations In most applications, the LTC3543 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3543 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance.
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To avoid the LTC3543 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = JA * PD where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3543 in dropout at an input voltage of 2.7V, an ambient temperature of 80C, and a load current of 600mA. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 80C is approximately 0.41. There, power dissipated by the part is: PD = ILOAD2 * RDS(ON) = 147.6mW For the DFN package, the JA is 64C/W. Thus, the junction temperature of the regulator is: TJ = 80C + 0.1476 * 64 = 89.4C which is well below the maximum junction temperature of 125C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability
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LTC3543 APPLICATIO S I FOR ATIO
problem. For a detailed explanation of the switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 * CLOAD. Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3543. These items are also illustrated graphically in Figures 5 and 6. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace, and the VIN trace should be kept short, direct and wide. 2. Does the VFB pin connect directly to the feedback voltage reference? Ensure that there is no load current running from the feedback reference voltage and the VFB pin. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the switching node, SW, away from the sensitive VFB node.
GND COUT CIN
VOUT
+
L
SW
4
CAP
5
MODE
6
1
2
3
C1
Figure 5. LTC3543 Layout Diagram
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5. Keep the (-) plates of CIN and COUT as close as possible. Design Example As a design example, assume the LTC3543 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 600mA, but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 1.5V. With this information we can calculate L using Equation 1, V V L = OUT * 1 - OUT f * IL VIN A 3.3H inductor works well for this application, yielding a ripple current of only 130mA. For best efficiency choose a 665mA or greater inductor with less than 0.05 series resistance. In Equation 2, CIN will require an RMS current rating of at least 0.3A at ILOAD(MAX)/2 at temperature. Using Equation 3, Selecting a 4.7F capacitor with an ESR of 0.05 for COUT yields an 8mV voltage ripple on the regulated output voltage. For feedback resistors, choose R1 = 402k. R2 can then be calculated using Equation 4. V R2 = OUT - 1 * R1 = 604k 0 . 6V Figure 6 shows the complete circuit along with its efficiency curve.
- + -
VIN VIN RUN VFB R1 R2
W
-
+
U
U
- +
CFWD
3543 F07
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LTC3543 APPLICATIO S I FOR ATIO U
GND VIN VIA TO R1 COUT CIN VIN GND
VOUT
VIA TO R2
L
SW
CAP
4
5
MODE C1
6
1
2
3
TYPICAL APPLICATIO S
Li-Ion BATTERY 2.7V TO 4.2V L 3.3H* VIN 10F LTC3543 PWR_EN RUN VFB R1 402k muRata GRM40X5R106K1H520 * TDK VLCF5020-3R3N1R6 ** TDK TDKC2012X5R0J475MT SW R2 604k 1.5V CFWD 10pF VOUT COUT 1.5V 4.7F**
EFFICIENCY (%)
VOUT AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV 20s/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 0V
3543 G22
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RUN VFB R1 R2 CFWD
VIA TO GND
VIA TO VOUT
3543 F08
Figure 6. LTC3543 Suggested Layout
MODE CAP GND
EXPOSED PAD
3543 TA02
100 90 80 70 60 50 40 30 20 10 0 0.1 VOUT = 1.5V 1 10 100 LOAD CURRENT (mA) 1000
3543 TA04
VIN = 4.2V VIN = 3.6V
VIN = 2.7V
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LTC3543 TYPICAL APPLICATIO U
Spread Spectrum Application
Li-Ion BATTERY 2.7V TO 4.2V L 3.3H* VIN 10F LTC3543 PWR_EN RUN VFB C1 2.2nF R1 402k muRata GRM40X5R106K1H520 * TDK VLCF5020-3R3N1R6 ** TDK TDKC2012X5R0J475MT SW R2 604k 1.5V CFWD 10pF VOUT COUT 1.5V 4.7F**
Output Noise Spectrum of a Conventional Buck Switching Converter (LTC3543 with Spread Spectrum Disabled) Showing Fundamental and Harmonic Frequencies
-10 -20 -30 AMPLITUDE (dBm) RBW = 3kHz
Output Noise Spectrum of the LTC3543 Spread Spectrum Buck Switching Converter. Note the Reduction in Fundamental and Harmonic Peak Spectral Amplitude Compared to Conventional Buck Switching Converter Output Noise
-10 -20 -30 AMPLITUDE (dBm) RBW = 3kHz
MODE CAP GND EXPOSED PAD
3543 TA08
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 VIN = 3.6V 1 10 100 LOAD CURRENT (mA) 1000
3543 TA11
-40 -50 -60 -70 -80 -90 -100 -110 0 6 18 12 FREQUENCY (MHz) 24 30
3543 TA09
-40 -50 -60 -70 -80 -90 -100 -110 0 6 18 12 FREQUENCY (MHz) 24 30
3543 TA10
0 0.1
PACKAGE DESCRIPTIO
3.55 0.05
1.65 0.05 (2 SIDES) PACKAGE OUTLINE PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 0.05 1 3.00 0.10 (2 SIDES) 1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 x 45 CHAMFER
(DCB6) DFN 0405
2.15 0.05
0.25 0.05 0.50 BSC 1.35 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 - 0.05
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DCB Package 6-Lead Plastic DFN (2mm x 3mm)
(Reference LTC DWG # 05-08-1715)
0.70 0.05 2.00 0.10 (2 SIDES) R = 0.115 TYP 4 6 0.40 0.10 R = 0.05 TYP 0.25 0.05 0.50 BSC 1.35 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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LTC3543 TYPICAL APPLICATIO U
PLL Application
Li-Ion BATTERY 2.7V TO 4.2V L 6.8H* VIN 10F LTC3543 PWR_EN RUN VFB C1 2.2nF R1 402k muRata GRM40X5R106K1H520 * CoEv DN4835-6R8 ** TDK TDKC2012X5R0J475MT SW R2 604k 1.5V CFWD 10pF VOUT COUT 1.5V 4.7F** INPUT CLOCK (1MHz) MODE CAP GND EXPOSED PAD INPUT CLOCK 2V/DIV
3543 TA05
100 90 80 70 EFFICIENCY (%)
SW 2V/DIV 200ns/DIV
60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3543 TA07
3543 TA06
RELATED PARTS
PART NUMBER LTC3405/LTC3405A LTC3406/LTC3406B LTC3407/LTC3407-2 LTC3409 LTC3410/LTC3410B LTC3411 LTC3441/LTC3442/ LTC3443 LTC3531/LTC3531-3/ LTC3531-3.3 LTC3532 LTC3542 LTC3547/LTC3547B LTC3548/LTC3548-1/ LTC3548-2 LTC3561 DESCRIPTION 300mA (IOUT), 1.5MHz, Synchrounous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchrounous Step-Down DC/DC Converter Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchrounous Step-Down DC/DC Converter 600mA (IOUT), 1.7MHz/2.6MHz, Synchrounous Step-Down DC/DC Converter COMMENTS 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD = <1A, ThinSOT Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD = <1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD = <1A, MS10E, DFN Packages 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65A, ISD = <1A, DFN Package
300mA (IOUT), 2.25MHz, Synchrounous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26A, DC/DC Converter ISD = <1A, SC70 Package 1.25A (IOUT), 4MHz, Synchrounous Step-Down DC/DC Converter 1.2A (IOUT), 2MHz, Synchrounous Buck-Boost DC/DC Converter 200mA (IOUT), 1.5MHz, Synchrounous Buck-Boost DC/DC Converter 500mA (IOUT), 2MHz, Synchrounous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD = <1A, MS10, DFN Packages 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50A, ISD = <1A, DFN Package 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16A, ISD = <1A, ThinSOT, DFN Packages 96% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35A, ISD = <1A, MS10, DFN Packages
500mA (IOUT), 2.25MHz, Synchrounous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 26A, DC/DC Converter ISD = <1A, 2mm x 2mm DFN, ThinSOT Packages Dual 300mA (IOUT), 2.25MHz, Synchrounous Step-Down DC/DC Converter Dual 400mA/800mA (IOUT), 2.25MHz, Synchrounous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD = <1A, DFN Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD = <1A, MS10E, DFN Packages 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240A, ISD = <1A, DFN Package
3543f LT 1206 * PRINTED IN USA
16 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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